A systematic investigation of the integrated effects of gate underlapping, dual work functionality and hetero gate dielectric for improved performance of CP TFETs
Crossref DOI link: https://doi.org/10.1007/s10825-017-1045-0
Published Online: 2017-08-22
Published Print: 2018-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Yadav, Dharmendra Singh
Sharma, Dheeraj
Tirkey, Sukeshni
Bajaj, Varun
License valid from 2017-08-22