Low Glitch & Low Power Dual Edge Triggered D-Type Flip Flops for Integrated Applications
Crossref DOI link: https://doi.org/10.35940/ijrte.B1044.078219
Published Online: 2019-07-30
Update policy: https://doi.org/10.35940/beiesp.crossmarkpolicy
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Pandey, Viresh
Jain, Pramod Kumar
Ajnar, Devendra Singh
