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Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Crossref DOI link: https://doi.org/10.1016/j.microrel.2013.08.011

Published Print: 2014-01

Update policy: https://doi.org/10.1016/elsevier_cm_policy

Authors

Chiu, Po-Yen

Ker, Ming-Dou
Funding

Funding for this research was provided by:

Ministry of Education

National Science Council (NSC 101-2220-E-009-020, NSC 101-2221-E-009-141)

National Chiao Tung University
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This article is maintained by: Elsevier

Article Title: Metal-layer capacitors in the 65nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Journal Title: Microelectronics Reliability

CrossRef DOI link to publisher maintained version: https://doi.org/10.1016/j.microrel.2013.08.011

Content Type: article

Copyright: Copyright © 2013 Elsevier Ltd. All rights reserved.