Mohamad, B.
Leroux, C.
Rideau, D.
Haond, M.
Reimbold, G.
Ghibaudo, G.
Funding for this research was provided by:
MINOS Laboratory of French ANR and WAYTOGO FAST ECSEL Project
This article is maintained by: Elsevier
Article Title: Reliable gate stack and substrate parameter extraction based on C-V measurements for 14nm node FDSOI technology
Journal Title: Solid-State Electronics
CrossRef DOI link to publisher maintained version: https://doi.org/10.1016/j.sse.2016.10.010
Content Type: article
Copyright: © 2016 Elsevier Ltd. All rights reserved.