Berthelon, R.
Andrieu, F.
Ortolland, S.
Nicolas, R.
Poiroux, T.
Baylac, E.
Dutartre, D.
Josse, E.
Claverie, A.
Haond, M.
Funding for this research was provided by:
French ministry of Industry
This article is maintained by: Elsevier
Article Title: Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology
Journal Title: Solid-State Electronics
CrossRef DOI link to publisher maintained version: https://doi.org/10.1016/j.sse.2016.10.011
Content Type: article
Copyright: © 2016 Elsevier Ltd. All rights reserved.