FPGA implementation of AAD pooling unit and performance analysis
Crossref DOI link: https://doi.org/10.30574/wjarr.2022.16.1.1085
Published Online: 2022-10-30
Update policy: https://doi.org/10.30574/wjarr.ourcrossmarkpolicy
Rajamahanti Meher Kiran,
Toram Naga Jahnavi,
Yarabati Mohana Rao,
Yamala Sudheer,
Udatha Prudhvi Naga Durgesh,
