Performance Analysis of Single- and Multi-Channel Distributed Arithmetic FIR Filter Architectures on FPGA
Crossref DOI link: https://doi.org/10.59256/ijsreat.20260604016
Published Online: 2026-07-27
Update policy: https://doi.org/10.59256/ijsreat/crossmark-policy-page
Nethra, M S
Dr, Manoj kumar S B
Srividya, C N
Smitha, M J
