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Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool

Crossref DOI link: https://doi.org/10.1007/978-3-030-31019-6_5

Published Online: 2019-10-09

Published Print: 2019

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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