Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits
Crossref DOI link: https://doi.org/10.1007/978-3-030-78841-4_15
Published Online: 2021-05-28
Published Print: 2022
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Peter, Steffen
Givargis, Tony
Text and Data Mining valid from 2021-05-28
Version of Record valid from 2021-05-28
Chapter History
First Online: 28 May 2021