A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme Using Simultaneously Copyable SRAM
Crossref DOI link: https://doi.org/10.1007/978-4-431-56594-9_25
Published Online: 2018-07-21
Published Print: 2019
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Yoshimoto, Masahiko
Matsukawa, Go
Nakata, Yohei
Kawaguchi, Hiroshi
Sugure, Yasuo
Oho, Shigeru
License valid from 2018-07-21