FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase
Crossref DOI link: https://doi.org/10.1007/978-981-10-5903-2_21
Published Online: 2018-04-11
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Singh, Arpita
Sharma, Abhay
Kumari, Priyanka
License valid from 2018-01-01