Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA
Crossref DOI link: https://doi.org/10.1007/978-981-10-8533-8_10
Published Online: 2018-05-16
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Agrawal, Tarun
Srivastava, Vivek
License valid from 2018-01-01