Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array
Crossref DOI link: https://doi.org/10.1007/978-981-10-8533-8_15
Published Online: 2018-05-16
Published Print: 2018
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Kaur, Inderpreet
Rohilla, Lakshay
Nagpal, Alisha
Pandey, Bishwajeet
Sharma, Sanchit
License valid from 2018-01-01