Delay and Crosstalk Aware Analysis for High Speed On-Chip Global RLC VLSI Interconnects
Crossref DOI link: https://doi.org/10.1007/978-981-16-0275-7_66
Published Online: 2021-09-10
Published Print: 2021
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Gupta, Apoorva
Maheshwari, Vikas
Malipatil, Somashekhar
Kar, Rajib
Text and Data Mining valid from 2021-01-01
Version of Record valid from 2021-01-01
Chapter History
First Online: 10 September 2021