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FPGA Implementation of Scaled “Quasi-Cyclic LDPC” Decoder Using High-Level Synthesis

Crossref DOI link: https://doi.org/10.1007/978-981-33-4389-4_14

Published Online: 2021-05-05

Published Print: 2021

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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