Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits
Crossref DOI link: https://doi.org/10.1007/s00034-016-0257-z
Published Online: 2016-02-16
Published Print: 2016-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Leela Rani, V.
Madhavi Latha, M.
Text and Data Mining valid from 2016-02-16