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2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Crossref DOI link: https://doi.org/10.1007/s00034-020-01594-5

Published Online: 2020-11-20

Published Print: 2021-06

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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