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A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology

Crossref DOI link: https://doi.org/10.1007/s00034-020-01639-9

Published Online: 2021-01-05

Published Print: 2021-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Moradinezhad Maryan, Mohammad https://orcid.org/0000-0003-2597-2079
Amini-Valashani, Majid https://orcid.org/0000-0001-8890-6496
Azhari, Seyed Javad https://orcid.org/0000-0001-9557-3095
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Text and Data Mining valid from 2021-01-05

Version of Record valid from 2021-01-05
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Article History

Received: 12 March 2020

Revised: 22 December 2020

Accepted: 24 December 2020

First Online: 5 January 2021