Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches
Crossref DOI link: https://doi.org/10.1007/s00034-021-01652-6
Published Online: 2021-02-13
Published Print: 2021-08
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Ramamurthy, Chinmaye http://orcid.org/0000-0001-7607-6974
Parikh, Chetan D.
Sen, Subhajit
Funding for this research was provided by:
ISRO University Research funding (RESPOND) program (DOS-2B-13012(2)/34/2017)
Text and Data Mining valid from 2021-02-13
Version of Record valid from 2021-02-13
Article History
Received: 16 July 2020
Revised: 9 January 2021
Accepted: 16 January 2021
First Online: 13 February 2021