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Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

Crossref DOI link: https://doi.org/10.1007/s00034-024-02835-7

Published Online: 2024-12-13

Published Print: 2025-04

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Roshanpanah, Abolfazl https://orcid.org/0000-0002-2335-8051
Torkzadeh, Pooya https://orcid.org/0000-0003-1646-7054
Hajsadeghi, Khosrow https://orcid.org/0000-0001-7465-6983
Dousti, Massoud https://orcid.org/0000-0003-2884-7062
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Text and Data Mining valid from 2024-12-13

Version of Record valid from 2024-12-13
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Article History

Received: 25 August 2023

Revised: 12 August 2024

Accepted: 14 August 2024

First Online: 13 December 2024

Declarations

:

: All authors declare that they have no conflicts of interest.

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