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Optimal Design of IEEE-754 Decimal Floating-Point Multipliers in FPGAs for DPD and BID Encoding

Published Online: 2025-10-03

Authors

Vázquez, Martín

Tosini, Marcelo

Leiva, Lucas https://orcid.org/0000-0002-4525-419X
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Text and Data Mining valid from 2025-10-03

Version of Record valid from 2025-10-03
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Article History

Received: 13 January 2025

Revised: 1 September 2025

Accepted: 3 September 2025

First Online: 3 October 2025

Declarations

:

: The authors have no relevant financial or non-financial interests to disclose.

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