Topology optimization for thermal stress reduction in power semiconductor module
Crossref DOI link: https://doi.org/10.1007/s00158-019-02341-4
Published Online: 2019-08-02
Published Print: 2019-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Matsumori, Tadayoshi http://orcid.org/0000-0001-9597-0285
Kawamoto, Atsushi
Kondoh, Tsuguo
Text and Data Mining valid from 2019-08-02
Version of Record valid from 2019-08-02
Article History
Received: 1 February 2019
Revised: 16 May 2019
Accepted: 24 June 2019
First Online: 2 August 2019
Compliance with Ethical Standards
:
: The authors declare that they have no conflict of interest.