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Authors
Lin, Chengqi
Ding, Junzhe
Chen, Jianlin
Wang, Yuan
Jiao, Jianhao
Mak, Pui-In
Wang, Nan
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Funding
Funding for this research was provided by:
Natural Science Foundation of Shanghai Municipality (25ZR1402143)
State Key Laboratory of Analog and Mixed-Signal VLSI (University of Macau) Open Research Project (SKL-AMSV/ORP/02/2025)
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Article History
Received: 14 September 2025
Accepted: 13 March 2026
First Online: 24 March 2026
Declarations
:
: The authors declare that they have no conflict of interest.
: Not applicable.
: Not applicable.
: Not applicable.
