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Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes

Crossref DOI link: https://doi.org/10.1007/s00500-020-05502-6

Published Online: 2021-01-16

Published Print: 2021-02

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Sugie, Yuya

Yoshida, Yuki https://orcid.org/0000-0002-1402-7840
Mertig, Normann https://orcid.org/0000-0003-3025-7141
Takemoto, Takashi https://orcid.org/0000-0002-5949-2252
Teramoto, Hiroshi

Nakamura, Atsuyoshi https://orcid.org/0000-0001-7078-8655
Takigawa, Ichigaku https://orcid.org/0000-0001-5633-995X
Minato, Shin-ichi

Yamaoka, Masanao

Komatsuzaki, Tamiki https://orcid.org/0000-0001-7175-8474
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Text and Data Mining valid from 2021-01-16

Version of Record valid from 2021-01-16
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Article History

First Online: 16 January 2021

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: The authors declare they have no conflict of interest.