Design of compressor-based multipliers using simulated annealing for arithmetic logic unit
Crossref DOI link: https://doi.org/10.1007/s00521-025-10981-5
Published Online: 2025-01-25
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Pavitra, Y. J.
Manikandan, J.
Text and Data Mining valid from 2025-01-25
Version of Record valid from 2025-01-25
Article History
Received: 2 October 2024
Accepted: 3 January 2025
First Online: 25 January 2025
Declarations
:
: The authors do not have any conflict of interest.