Design and power analysis of 4 × 4 semiconductor ROM array with row decoder and column decoder at 32, 22 and 16 nm channel length of MOS transistor
Crossref DOI link: https://doi.org/10.1007/s00542-016-2875-6
Published Online: 2016-02-18
Published Print: 2017-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Bari, Surajit https://orcid.org/0000-0003-3531-4950
Bhowmik, Sonali
De, Debashis
Sarkar, Angsuman
Text and Data Mining valid from 2016-02-18
