Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors
Crossref DOI link: https://doi.org/10.1007/s00542-016-3049-2
Published Online: 2016-06-29
Published Print: 2017-07
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Roy, Debapriya
Biswas, Abhijit
License valid from 2016-06-29
