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Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

Crossref DOI link: https://doi.org/10.1007/s00542-017-3642-z

Published Online: 2017-12-04

Published Print: 2019-05

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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