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A CAD approach for suppression of power supply noise and performance analysis of some multi-core processors in pre-layout stage

Crossref DOI link: https://doi.org/10.1007/s00542-018-4043-7

Published Online: 2018-07-24

Published Print: 2019-05

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Mitra, Partha https://orcid.org/0000-0002-1331-3538
Bhaumik, Jaydeb
License Information

Text and Data Mining valid from 2018-07-24
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Article History

Received: 30 July 2017

Accepted: 9 July 2018

First Online: 24 July 2018