A power efficient PFD-CP architecture for high speed clock and data recovery application
Crossref DOI link: https://doi.org/10.1007/s00542-019-04458-4
Published Online: 2019-05-08
Published Print: 2019-12
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Maiti, Madhusudan
Saw, Suraj Kumar
Nath, Vijay
Majumder, Alak http://orcid.org/0000-0003-4775-8591
Funding for this research was provided by:
Ministry of Electronics and Information technology (9(1)/2014-MDD)
Text and Data Mining valid from 2019-05-08
Article History
Received: 14 February 2019
Accepted: 29 April 2019
First Online: 8 May 2019