Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs
Crossref DOI link: https://doi.org/10.1007/s00542-023-05464-3
Published Online: 2023-05-11
Published Print: 2023-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Maity, Raj Kumar
Samanta, Jagannath http://orcid.org/0000-0003-1168-1166
Bhaumik, Jaydeb
Text and Data Mining valid from 2023-05-11
Version of Record valid from 2023-05-11
Article History
Received: 31 March 2022
Accepted: 27 April 2023
First Online: 11 May 2023