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Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology

Crossref DOI link: https://doi.org/10.1007/s00542-024-05667-2

Published Online: 2024-04-21

Published Print: 2025-02

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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