Dielectric pocket engineered, gate induced drain leakages (GIDL) and analog performance analysis of dual metal nanowire ferroelectric MOSFET (DPE-DM-NW-Fe FET) as an inverter
Crossref DOI link: https://doi.org/10.1007/s00542-024-05681-4
Published Online: 2024-05-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Garg, Shalu
Kaur, Jasdeep
Goel, Anubha
Haldar, Subhasis
Gupta, R. S.
Text and Data Mining valid from 2024-05-09
Version of Record valid from 2024-05-09
Article History
Received: 10 October 2023
Accepted: 19 April 2024
First Online: 9 May 2024
Declarations
:
: The authors declare no competing interests.