Controller synthesis for linear temporal logic and steady-state specifications
Crossref DOI link: https://doi.org/10.1007/s10458-024-09648-7
Published Online: 2024-05-03
Published Print: 2024-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Velasquez, Alvaro
Alkhouri, Ismail
Beckus, Andre
Trivedi, Ashutosh
Atia, George
Text and Data Mining valid from 2024-05-03
Version of Record valid from 2024-05-03
Article History
Accepted: 8 April 2024
First Online: 3 May 2024
Declarations
:
: The authors declare no Conflict of interest.