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Design of a 3-channel 5 Gb/s/ch deserializer array for high-speed parallel links

Crossref DOI link: https://doi.org/10.1007/s10470-014-0454-2

Published Online: 2014-11-19

Published Print: 2015-01

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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