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Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

Crossref DOI link: https://doi.org/10.1007/s10470-015-0553-8

Published Online: 2015-05-17

Published Print: 2015-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy