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Erratum to: Design of new practical phase shaping circuit using optimal pole–zero interlacing algorithm for fractional order PID controller

Crossref DOI link: https://doi.org/10.1007/s10470-017-0946-y

Published Online: 2017-02-20

Published Print: 2017-04

Update policy: https://doi.org/10.1007/springer_crossmark_policy

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