A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors
Crossref DOI link: https://doi.org/10.1007/s10470-017-0982-7
Published Online: 2017-04-22
Published Print: 2017-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Zhou, Zhijun
Warr, Paul
License valid from 2017-04-22