56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology
Crossref DOI link: https://doi.org/10.1007/s10470-018-1186-5
Published Online: 2018-04-09
Published Print: 2018-09
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Wang, Chua-Chin http://orcid.org/0000-0002-2426-2879
Wang, Deng-Shain
Chen, Sih-Yu
Text and Data Mining valid from 2018-04-09
Article History
Received: 14 August 2017
Revised: 7 March 2018
Accepted: 4 April 2018
First Online: 9 April 2018