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Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Crossref DOI link: https://doi.org/10.1007/s10470-018-1277-3

Published Online: 2018-07-31

Published Print: 2019-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Gavaskar, K. https://orcid.org/0000-0001-6560-0734
Ragupathy, U. S.
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Text and Data Mining valid from 2018-07-31
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Article History

Received: 8 July 2017

Revised: 25 July 2018

Accepted: 26 July 2018

First Online: 31 July 2018