High speed RLC equivalent RC delay model for global VLSI interconnects
Crossref DOI link: https://doi.org/10.1007/s10470-019-01398-x
Published Online: 2019-01-22
Published Print: 2019-07
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Jadav, Sunil
vashishath, Munish
Chandel, Rajeevan
Text and Data Mining valid from 2019-01-22
Article History
Received: 8 September 2018
Revised: 1 January 2019
Accepted: 12 January 2019
First Online: 22 January 2019