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A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

Crossref DOI link: https://doi.org/10.1007/s10470-020-01597-x

Published Online: 2020-02-04

Published Print: 2020-03

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Sofimowloodi, Sobhan

Razaghian, Farhad https://orcid.org/0000-0001-9005-4309
Gholami, Mohammad
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Text and Data Mining valid from 2020-02-04

Version of Record valid from 2020-02-04
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Article History

Received: 2 October 2019

Revised: 2 October 2019

Accepted: 28 January 2020

First Online: 4 February 2020