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A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme

Crossref DOI link: https://doi.org/10.1007/s10470-022-02016-z

Published Online: 2022-05-10

Published Print: 2022-07

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Jung, Inho

Bae, Sunghyun

Lee, Sinho

Lee, Minjae https://orcid.org/0000-0003-1500-1404
Funding

Funding for this research was provided by:

National Research Foundation of Korea (2019R1A2B5B01069415)

Samsung Electronics
License Information

Text and Data Mining valid from 2022-05-10

Version of Record valid from 2022-05-10
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Article History

Received: 15 December 2020

Revised: 13 December 2021

Accepted: 21 February 2022

First Online: 10 May 2022

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