VCSEL driver with synthesis of 25-Gb/s PAM-4 signal in 90-nm CMOS technology
Crossref DOI link: https://doi.org/10.1007/s10470-022-02111-1
Published Online: 2022-11-23
Published Print: 2023-03
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Jou, Jau-Ji https://orcid.org/0000-0002-2172-9912
Shih, Tien-Tsorng
Wu, Tsung-Yen
Funding for this research was provided by:
Ministry of Science and Technology, Taiwan (MOST 110-2224-E-992-001)
Text and Data Mining valid from 2022-11-23
Version of Record valid from 2022-11-23
Article History
Received: 4 January 2022
Revised: 10 November 2022
Accepted: 11 November 2022
First Online: 23 November 2022