A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance
Crossref DOI link: https://doi.org/10.1007/s10470-023-02147-x
Published Online: 2023-02-03
Published Print: 2023-04
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Rawat, Bhawna
Mittal, Poornima http://orcid.org/0000-0002-9479-8628
Text and Data Mining valid from 2023-02-03
Version of Record valid from 2023-02-03
Article History
Received: 13 November 2021
Revised: 28 May 2022
Accepted: 18 January 2023
First Online: 3 February 2023