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Glitch free transmission gate based linear and nonlinear PFD architectures for fast and low reference-spur PLL

Crossref DOI link: https://doi.org/10.1007/s10470-025-02354-8

Published Online: 2025-02-28

Published Print: 2025-04

Update policy: https://doi.org/10.1007/springer_crossmark_policy

Authors

Sivaraaj, N. R. https://orcid.org/0009-0001-4987-2518
Majeed, K. K. Abdul https://orcid.org/0000-0001-9755-1471
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Text and Data Mining valid from 2025-02-28

Version of Record valid from 2025-02-28
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Article History

Received: 19 April 2023

Revised: 6 February 2025

Accepted: 7 February 2025

First Online: 28 February 2025

Declarations

:

: The authors declare that they have no conflict of interest.