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Triple metal gate vertical TFET with SiGe/Si heterojunction for high-performance and low-power VLSI circuits

Published Online: 2026-04-04

Published Print: 2026-04

Authors

Mohanta, Debasish

Singh, Sruti Suvadarsini

Sahu, Prasanna Kumar
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Text and Data Mining valid from 2026-04-01

Version of Record valid from 2026-04-01
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Article History

Received: 15 December 2025

Revised: 15 February 2026

Accepted: 20 March 2026

First Online: 4 April 2026

Declarations

:

: The authors declare no competing interests.

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