A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system
Crossref DOI link: https://doi.org/10.1007/s10586-018-2513-4
Published Online: 2018-03-27
Published Print: 2019-11
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Krishnamoorthy, Raja
Saravanan, S.
Text and Data Mining valid from 2018-03-27
Article History
Received: 19 February 2018
Revised: 28 February 2018
Accepted: 12 March 2018
First Online: 27 March 2018