Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications
Crossref DOI link: https://doi.org/10.1007/s10617-019-09225-2
Published Online: 2019-11-05
Published Print: 2020-06
Update policy: https://doi.org/10.1007/springer_crossmark_policy
Hanuman, C. R. S.
Kamala, J.
Aruna, A. R.
Text and Data Mining valid from 2019-11-05
Version of Record valid from 2019-11-05
Article History
Received: 19 May 2019
Accepted: 20 October 2019
First Online: 5 November 2019