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Authors
Nhivekar, Ganesh S. https://orcid.org/0000-0002-6616-6586
Khandait, Pallavi D.
Kamble, Santosh B.
Kamat, Rajanish K.
Dongale, Tukaram D. https://orcid.org/0000-0003-2536-6132
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Funding
Funding for this research was provided by:
Yashavantrao Chavan Institute of Science, Satara
Rashtriya Uchchatar Shiksha Abhiyan (RUSA-Industry Sponsored Centre for VLSI System Design, RUSA-Industry Sponsored Centre for VLSI System Design)
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Article History
Accepted: 21 July 2025
First Online: 7 August 2025
Declarations
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: The authors declare no competing interests.
